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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. december 1995 copyright ? intel corporation, 1995 order number: 271312-002 VS28F016SV, ms28f016sv 16-mbit (1-mbit x 16, 2-mbit x 8) flashfile tm memory y VS28F016SV e b 40 cto a 125 c e se2 grade y ms28f016sv e b 55 cto a 125 c e qml certified e se1 grade y smartvoltage technology e user-selectable 3.3v or 5v v cc e user-selectable 5v or 12v v pp y three voltage/speed options e 80 ns access time, 5.0v g 5% e 85 ns access time, 5.0v g 10% e 120 ns access time, 3.3v g 10% y 1 million erase cycles per block typical y 14.3 mb/sec burst write transfer rate y configurable x8 or x16 operation y 56-lead ssop plastic package y backwards-compatible with ve28f008, m28f008 and 28f016sa command set y revolutionary architecture e multiple command execution e write during erase e command super-set of the intel ve28f008, m28f008 e page buffer write y multiple power savings modes y two 256-byte page buffers y state-of-the-art 0.6 m m etox tm iv flash technology intel's vs/ms28f016sv, 16-mbit flashfiie tm memory is the latest member of intel's high density, high per- formance memory family for the industrial, special environment, and military markets. its user selectable v cc and v pp (smartvoltage technology), innovative capabilities, 100% compatibility with the ve28f008 and m28f008, multiple power savings modes, selective block locking, and very fast read/write performance make it the ideal choice for any applications that need a high density and a wide temperature range memory device. the vs/ms28f016sv is the ideal choice for designers who need to break free from the dependence on slow rotating media or battery backed up memory arrays. with two product grades (se1: b 55 cto a 125 c, and se2: b 40 cto a 125 c) available, the vs/ms28f016sv is perfect for the non-pc industries like telecommunications, embedded/industrial, auto- motive, navigation, wireless communication, commercial aircraft, and all military programs. the vs/ms28f016sv's x8/x16 architecture allows for the optimization of the memory to processor interface. the flexible block locking options enable bundling of executable application software in a resident flash array (rfa), pcmcia memory or ata cards or memory modules. the vs/ms28f016sv is offered in a 56-lead ss0p (shrink small outline package) and is manufactured on intel's 0.6 m m etox tm iv process technology.
VS28F016SV, ms28f016sv flashfile tm memory contents page 1.0 introduction 3 1.1 enhanced features 3 1.2 product overview 3 2.0 device pinout 5 2.1 lead descriptions 7 3.0 memory maps 10 3.1 extended status registers memory map 11 4.0 bus operations, commands and status register definitions 12 4.1 bus operations for word-wide mode (byte y e v ih ) 12 4.2 bus operations for byte-wide mode (byte y e v il ) 12 4.3 ve28f008 or m28f008 compatible mode command bus definitions 13 4.4 vs/ms28f016sv-performance enhancement command bus definitions 14 4.5 compatible status register 16 4.6 global status register 17 4.7 block status register 18 4.8 device configuration code 19 contents page 5.0 electrical specifications 20 5.1 absolute maximum ratings 20 5.2 capacitance 21 5.3 timing nomenclature 22 5.4 dc characteristics (v cc e 3.3v g 0.5v) 25 5.5 dc characteristics (v cc e 5.0v g 0.5v) 28 5.6 ac characteristicseread only operations 31 5.7 power-up and reset timings 35 5.8 ac characteristics for we y econtrolled command write operations 36 5.9 ac characteristics for ce y econtrolled command write operations 39 5.10 ac characteristics for we y econtrolled page buffer write operations 42 5.11 ac characteristics for ce y econtrolled page buffer write operations 44 5.12 erase and word/byte write performance 45 6.0 mechanical specifications 47 device nomenclature 48 additional information 48 data sheet revision history 48 2
VS28F016SV, ms28f016sv flashfile tm memory 1.0 introduction the documentation of the intel vs/ms28f016sv memory device includes this data sheet, a detailed user's manual, and a number of application notes, all of which are referenced at the end of this data sheet. the data sheet is intended to give an overview of the chip feature-set and of the operating ac/dc specifications. the 28f016sa (compatible with vs/ms28f016sv) user's manual provides com- plete descriptions of the user modes, system inter- face examples and detailed descriptions of all princi- ples of operation. it also contains the full list of software algorithm flowcharts, and a brief section on compatibility with the intel ve28f008 and m28f008. 1.1 enhanced features the vs/ms28f016sv is backwards compatible with the ve28f008 and m28f008 and offers the follow- ing enhancements: # smartvoltage technology e selectable 5.0v or 12.0v v pp # v pp level bit in block status register # additional ry/by y configuration e pulse-on-write/erase # additional upload device information command feedback e device revision number e device proliferation code e device configuration code # x8/x16 architecture # block locking # 2 page buffers # instruction queuing 1.2 product overview the vs/ms28f016sv is a high-performance, 16-mbit (16,777,216-bit) block erasable, non-volatile random access memory, organized as either 1 mword x 16 or 2 mbyte x 8. the vs/ms28f016sv includes thirty-two 64-kb (65,536 byte) blocks or thirty-two 32-kw (32,768 word) blocks. a chip mem- ory map is shown in figure 3. the implementation of a new architecture, with many enhanced features, will improve the device op- erating characteristics and result in greater product reliability and ease of use. the vs/ms28f016sv incorporates smartvoltage technology, providing v cc operation at both 3.3v and 5.0v and program and erase capability at v pp e 12.0v or 5.0v. operating at v cc e 3.3v, the vs/ms28f016sv consumes approximately one-half the power consumption at 5.0v v cc , while 5.0v v cc provides highest read performance capability. v pp e 5.0v operation eliminates the need for a separate 12.0v converter, while v pp e 12.0v maximizes write/erase performance. in addition to the flexible program and erase voltages, the dedicated v pp gives complete code protection with v pp s v pplk . depending on system design specifications, the vs/ms28f016sv is capable of supporting e 80 ns access times with a v cc of 5.0v g 5% and loading of 30 pf e 85 ns access times with a v cc of 5.0v g 10% and loading of 100 pf e 120 ns access times with a v cc of 3.3v g 5% and loading of 50 pf a 3/5 y input pin configures the device's internal cir- cuitry for optimal 3.3v or 5.0v read/write operation. a command user interface (cui) serves as the sys- tem interface between the microprocessor or micro- controller and the internal memory operation. internal algorithm automation allows byte/word writes and block erase operations to be executed using a two-write command sequence to the cui in the same way as the ve28f008 or m28f008 8-mbit flashfile memory. a super-set of commands has been added to the basic ve28f008 or m28f008 command-set to achieve higher write performance and provide addi- tional capabilities. these new commands and fea- tures include: # page buffer writes to flash # command queuing capability # automatic data writes during erase # software locking of memory blocks # two-byte successive writes in 8-bit systems # erase all unlocked blocks 3
VS28F016SV, ms28f016sv flashfile tm memory writing of memory data is performed in either byte or word increments typically within 6 m sec (12.0v v pp ) b a 33% improvement over the ve28f008 or m28f008. a block erase operation erases one of the 32 blocks in about 1.0 sec (12.0v v pp ), indepen- dent of the other blocks, which is about a 65% im- provement over the ve28f008 or m28f008. each block can be written and erased a minimum of 100,000 cycles. systems can achieve one million block erase cycles by providing wear-leveling algo- rithms and graceful block retirement. these tech- niques have already been employed in many flash file systems and hard disk drive designs. the vs/ms28f016sv incorporates two page buff- ers of 256 bytes (128 words) each to allow page data writes. this feature can improve a system write performance by up to 4.8 times over previous flash memory devices, which have no page buffers. all operations are started by a sequence of write commands to the device. three status registers (described in detail later in this data sheet) and a ry/by y output pin provide information on the prog- ress of the requested operation. while the ve28f008 or m28f008 requires an opera- tion to complete before the next operation can be requested, the vs/ms28f016sv allows queuing of the next operation while the memory executes the current operation. this eliminates system overhead when writing several bytes in a row to the array or erasing several blocks at the same time. the vs/ms28f016sv can also perform write operations to one block of memory while performing erase of another block. the vs/ms28f016sv provides selectable block locking to protect code or data such as device driv- ers, pcmcia card information, rom-executable o/s or application code. each block has an associ- ated non-volatile lock-bit which determines the lock status of the block. in addition, the vs/ms28f016sv has a master write protect pin (wp y ) which prevents any modifications to memory blocks whose lock-bits are set. the vs/ms28f016sv contains three types of status registers to accomplish various functions: # a compatible status register (csr) which is 100% compatible with the ve28f008 or m28f008 flashfile memory status register. the csr, when used alone, provides a straightfor- ward upgrade capability to the vs/ms28f016sv from a ve28f008- or m28f008-based design. # a global status register (gsr) which informs the system of command queue status, page buffer status, and overall write state machine (wsm) status. # 32 block status registers (bsrs) which provide block-specific status information such as the block lock-bit status. the gsr and bsr memory maps for byte-wide and word-wide modes are shown in figures 4 and 5. the vs/ms28f016sv incorporates an open drain ry/by y output pin. this feature allows the user to or-tie many ry/by y pins together in a multiple memory configuration such as a resident flash ar- ray. other configurations of the ry/by y pin are en- abled via special cui commands and are described in detail in the 16-mbit flash product family user's manual. the vs/ms28f016sv's upload device information command is enhanced compared to the ve28f008 or m28f008, providing access to additional device information. this command uploads the device re- vision number, device proliferation code and de- vice configuration code. the device proliferation code for the vs/ms28f016sv is 01h, and the de- vice configuration code identifies the current ry/by y configuration. section 4.4 documents the exact page buffer address locations for all uploaded information. a subsequent page buffer swap and page buffer read command sequence is necessary to read the correct device information. the vs/ms28f016sv also incorporates a dual chip- enable function with two input pins, ce 0 y and ce 1 y . these pins have exactly the same functional- ity as the regular chip-enable pin, ce y ,onthe ve28f008 or m28f008. for minimum chip designs, ce 1 y may be tied to ground and system logic may use ce 0 y as the chip enable input. the vs/ms28f016sv uses the logical combination of these two signals to enable or disable the entire chip. both ce 0 y and ce 1 y must be active low to enable the device. if either one becomes inactive, the chip will be disabled. this feature, along with the open drain ry/by y pin, allows the system designer to reduce the number of control pins used in a large array of 16-mbit devices. the byte y pin allows either x8 or x16 read/writes to the vs/ms28f016sv. byte y at logic low se- lects 8-bit mode with address a 0 selecting between low byte and high byte. on the other hand, byte y 4
VS28F016SV, ms28f016sv flashfile tm memory at logic high enables 16-bit operation with address a 1 becoming the lowest order address and address a 0 is not used (don't care). a device block diagram is shown in figure 1. the vs/ms28f016sv is specified for a maximum access time of 80 ns (t acc ) at 5.0v operation (4.75v to 5.25v) in either the se1 or se2 grades. a corre- sponding maximum access time of 120 ns at 3.3v (3.15v to 3.45v) is achieved for reduced power con- sumption applications. the vs/ms28f016sv incorporates an automatic power saving (aps) feature which substantially re- duces the active current when the device is in static mode of operation (addresses not switching). in aps mode, the typical i cc current is 1 ma at 5.0v (0.8 ma at 3.3v). a deep power-down mode of operation is invoked when the rp y (called pwd y on the ve28f008 or m28f008) pin transitions low. this mode brings the device power consumption to less than 30.0 m a, typ- ically, and provides additional write protection by acting as a device reset pin during power transitions. a reset time of 500 ns (5.0v v cc operation) is re- quired from rp y switching high until outputs are again valid. in the deep power-down state, the wsm is reset (any current operation will abort) and the csr, gsr and bsr registers are cleared. a cmos standby mode of operation is enabled when either ce 0 y or ce 1 y transitions high and rp y stays high with all input control pins at cmos levels. in this mode, the device typically draws an i cc standby current of 70 m aat5vv cc . 2.0 device pinout the vs/ms28f016sv 56l-ssop pinout configura- tion is shown in figure 2. 5
VS28F016SV, ms28f016sv flashfile tm memory 271312 21 figure 1. block diagram 6
VS28F016SV, ms28f016sv flashfile tm memory 2.1 lead descriptions symbol type name and function a 0 input byte-select address: selects between high and low byte when device is in x8 mode. this address is latched in x8 data writes. not used in x16 mode (i.e., the a 0 input buffer is turned off when byte y is high). a 1 -a 15 input word-select addresses: select a word within one 64-kbyte block. a 6-15 selects 1 of 1024 rows, and a 1-5 selects 16 of 512 columns. these addresses are latched during data writes. a 16 -a 20 input block-select addresses: select 1 of 32 erase blocks. these addresses are latched during data writes, erase and lock-block operations. dq 0 -dq 7 input/output low-byte data bus: inputs data and commands during cui write cycles. outputs array, buffer, identifier or status data in the appropriate read mode. floated when the chip is de-selected or the outputs are disabled. dq 8 -dq 15 input/output high-byte data bus: inputs data during x16 data-write operations. outputs array, buffer or identifier data in the appropriate read mode; not used for status register reads. floated when the chip is de-selected or the outputs are disabled. ce 0 y ,ce 1 y input chip enable inputs: activate the device's control logic, input buffers, decoders and sense amplifiers. with either ce 0 y or ce 1 y high, the device is de-selected and power consumption reduces to standby levels upon completion of any current data-write or erase operations. both ce 0 y ,ce 1 y must be low to select the device. all timing specifications are the same for both signals. device selection occurs with the latter falling edge of ce 0 y or ce 1 y . the first rising edge of ce 0 y or ce 1 y disables the device. rp y input reset/power-down: rp y low places the device in a deep power-down state. all circuits that consume static power, even those circuits enabled in standby mode, are turned off. when returning from deep power-down, a recovery time of t phqv at 5.0v v cc is required to allow these circuits to power-up. when rp y goes low, any current or pending wsm operation(s) are terminated, and the device is reset. all status registers return to ready (with all status flags cleared). exit from deep power-down places the device in read array mode. oe y input output enable: gates device data through the output buffers when low. the outputs float to tri-state off when oe y is high. note: ce x y overrides oe y , and oe y overrides we y . we y input write enable: controls access to the cui, page buffers, data queue registers and address queue latches. we y is active low, and latches both address and data (command or array) on its rising edge. page buffer addresses are latched on the falling edge of we y . 7
VS28F016SV, ms28f016sv flashfile tm memory 2.1 lead descriptions (continued) symbol type name and function ry/by y open drain ready/busy: indicates status of the internal wsm. when low, it indicates that the wsm is busy performing an operation. ry/by y floating indicates output that the wsm is ready for new operations (or wsm has completed all pending operations), or erase is suspended, or the device is in deep power- down mode. this output is always active (i.e., not floated to tri-state off when oe y or ce 0 y ,ce 1 y are high), except if a ry/by y pin disable command is issued. wp y input write protect: erase blocks can be locked by writing a nonvolatile lock- bit for each block. when wp y is low, those locked blocks as reflected by the block-lock status bits (bsr.6), are protected from inadvertent data writes or erases. when wp y is high, all blocks can be written or erased regardless of the state ot the lock-bits. the wp y input buffer is disabled when rp y transitions low (deep power-down mode). byte y input byte enable: byte y low places device in x8 mode. all data is then input or output on dq 07 , and dq 815 float. address a 0 selects between the high and low byte. byte y high places the device in x16 mode, and turns off the a 0 input buffer. address a 1 , then becomes the lowest order address. 3/5 y input 3.3/5.0 volt select: 3/5 y high configures internal circuits for 3.3v operation. 3/5 y low configures internal circuits for 5.0v operation. note: reading the array with 3/5 y high in a 5.0v system could damage the device. reference the power-up and reset timings (section 5.7) for 3/5 y switching delay to valid data. v pp supply write/erase power supply (12.0v g 0.6v, 5.0v g 0.5v): for erasing memory array blocks or writing words/bytes/pages into the flash array. v pp e 5.0v g 0.5v eliminates the need for a 12v converter, while connection to 1 2.0v g 0.6v maximizes write/erase performance. note: successful completion of write and erase attempts is inhibited with v pp at or below 1.5v. write and erase attempts with v pp between 1.5v and 4.5v, between 5.5v and 11.4v, and above 12.6v produce spurious results and should not be attempted. v cc supply device power supply (3.3v g 0.45v, 5.0v g 0.5v, 5.0 g 0.25v): to switch 3.3v to 5.0v (or vice versa), first ramp v cc down to gnd, and then power to the new v cc voltage. do not leave any power pins floating. gnd supply ground for all internal circuitry: do not leave any ground pins floating. nc no connect: lead may be driven or left floating. 8
VS28F016SV, ms28f016sv flashfile tm memory 271312 2 24mm x 13.5mm 0.8mm lead pitch top view note: 56-lead ssop mechanical diagrams and dimensions are shown at the end of this data sheet. figure 2. ssop pinout configuration 9
VS28F016SV, ms28f016sv flashfile tm memory 3.0 memory maps 271312 3 figure 3. vs/ms28f016sv memory maps (byte-wide and word-wide modes) 10
VS28F016SV, ms28f016sv flashfile tm memory 3.1 extended status registers memory map 271312 4 figure 4. extended status register memory map (byte-wide mode) 271312 5 figure 5. extended status register memory map (word-wide mode) 11
VS28F016SV, ms28f016sv flashfile tm memory 4.0 bus operations, commands and status register definitions 4.1 bus operations for word-wide mode (byte y e v ih ) mode notes rp y ce 1 y ce 0 y oe y we y a 1 dq 0-15 ry/by y read 1,2,7 v ih v il v il v il v ih xd out x output disable 1,6,7 v ih v il v il v ih v ih x high z x standby 1,6,7 v ih v il v ih x x x high z x v ih v il v ih v ih deep power-down 1,3 v il x x x x x high z v oh manufacturer id 4 v ih v il v il v il v ih v il 0089h v oh device id 4 v ih v il v il v il v ih v ih 66a0h v oh write 1,5,6 v ih v il v il v ih v il xd in x 4.2 bus operations for byte-wide mode (byte y e v il ) mode notes rp y ce 1 y ce 0 y oe y we y a 0 dq 0-7 ry/by y read 1,2,7 v ih v il v il v il v ih xd out x output disable 1,6,7 v ih v il v il v ih v ih x high z x standby 1,6,7 v ih v il v ih x x x high z x v ih v il v ih v ih deep power-down 1,3 v il x x x x x high z v oh manufacturer id 4 v ih v il v il v il v ih v il 89h v oh device id 4 v ih v il v il v il v ih v ih a0h v oh write 1,5,6 v ih v il v il v ih v il xd in x notes: 1. x can be v ih or v il for address or control pins except for ry/by y , which is either v ol or v oh . 2. ry/by y output is open drain. when the wsm is ready, erase is suspended or the device is in deep power-down mode. ry/by y will be at v oh if it is tied to v cc through a resistor. ry/by y at v oh is independent of oe y while a wsm operation is in progress. 3. rp y at gnd g 0.2v ensures the lowest deep power-down current. 4. a 0 and a 1 at v il provide device manufacturer codes in x8 and x16 modes respectively. a 0 and a 1 at v ih provide device id codes in x8 and x16 modes respectively. all other addresses are set to zero. 5. commands for erase, data write, or lock-block operations can only be completed successfully when v pp e v pph1 or v pp e v pph2 . 6. while the wsm is running, ry/by y in level-mode (default) stays at v ol until all operations are complete. ry/by y goes to v oh when the wsm is not busy or in erase suspend mode. 7. ry/by y may be at v ol while the wsm is busy performing various operations. for example, a status register read during a write operation. 12
VS28F016SV, ms28f016sv flashfile tm memory 4.3 ve28f008 and m28f008 compatible mode command bus definitions command notes first bus cycle second bus cycle oper addr data (4) oper addr data (4) read array write x xxffh read aa ad intelligent identiier 1 write x xx90h read ia id read compatible status register 2 write x xx70h read x csrd clear status register 3 write x xx50h word/byte write write x xx40h write wa wd alternate word/byte write write x xx10h write wa wd block erase/confirm write x xx20h write ba xxd0h erase suspend/resume write x xxb0h write x xxd0h address data aa e array address ad e array data ba e block address csrd e csr data ia e ldentitier address id e identifier data wa e write address wd e write data x e don't care notes: 1. following the intelligent identifier command, two read operations access the manutacturer and device signature codes. 2. the csr is automatically available after device enters data write, erase, or suspend operations. 3. clears csr.3, csr.4 and csr.5. also clears gsr.5 and all bsr.5, bsr.4 and bsr.2 bits. see status register defini- tions. 4. the upper byte of the data bus (dq 815 ) during command writes is a ``don't care'' in x16 operation of the device. 13
VS28F016SV, ms28f016sv flashfile tm memory 4.4 vs/ms28f016sveperformance enhancement command bus definitions command mode notes first bus cycle second bus cycle third bus cycle oper addr data (13) oper addr data (13) oper addr data read extended 1 write x xx71h read ra gsrd status register bsrd page buffer swap 7 write x xx72h read page buffer write x xx75h read pa pd single load to write x xx74h write pa pd page buffer sequential load to x8 4,6,10 write x xxe0h write x bcl write x bch page buffer x16 4,5,6,10 write x xxe0h write x wcl write x wch page buffer write x8 3,4,9,10 write x xx0ch write a 0 bc(l,h) write wa bc(h,l) to flash x16 4,5,10 write x xx0ch write x wcl write wa wch two-byte write x8 3 write x xxfbh write a 0 wd(l,h) write wa wd(h,l) lock block/ write x xx77h write ba xxd0h confirm upload status 2 write x xx97h write x xxd0h bits/confirm upload device 11 write x xx99h write x xxd0h information/ confirm erase all unlocked write x xxa7h write x xxd0h blocks/confirm ry/by y enable to 8 write x xx96h write x xx01h level-mode ry/by y pulse- 8 write x xx96h write x xx02h on-write ry/by y pulse- 8 write x xx96h write x xx03h on-erase ry/by y disable 8 write x xx96h write x xx04h ry/by y pulse- 8 write x xx96h write x xx05h on-write/erase sleep 12 write x xxf0h abort write x xx80h address ba e block address pa e page butter address ra e extended register address wa e write address x e don't care data ad e array data pd e page buffer data bsrd e bsr data gsrd e gsr data wc (l,h) e word count (low, high) bc (l,h) e byte count (low, high) wd (l,h) e write data (low, high) 14
VS28F016SV, ms28f016sv flashfile tm memory notes: 1. ra can be the gsr address or any bsr address. see figures 4 and 5 for extended status register memory maps. 2. upon device power-up, all bsr lock-bits come up locked. the upload status bits command must be written to reflect the actual lock-bit status. 3. a 0 is automatically complemented to load second byte of data. byte y must be at v il .a 0 value determines which wd/bc is supplied first: a 0 e 0 looks at the wdl/bcl, a 0 e 1 looks at the wdh/bch. 4. bch/wch must be at 00h for this product because of the 256-byte (128-word) page buffer size, and to avoid writing the page buffer contents to more than one 256-byte segment within an array block. they are simply shown for future page buffer expandability. 5. in x16 mode, only the lower byte dq 0-7 is used for wcl and wch. the upper byte dq 8-15 is a don't care. 6. pa and pd (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown. 7. this command allows the user to swap between available page buffers (0 or 1). 8. these commands reconfigure ry/by y output to one of two pulse-modes or enable and disable the ry/by y function. 9. write address, wa, is the destination address in the flash array which must match the source address in the page buffer. refer to the 16-mbit flash product family user's manual. 10. bcl e 00h corresponds to a byte count of 1. similarly, wcl e 00h corresponds to a word count of 1. 11. after writing the upload device information command and the confirm command, the following information is output at page buffer addresses specified below: address information 06h, 07h (byte mode) device revision number 03h (word mode) device revision number 1eh (byte mode) device configuration code 0fh (dq 07 ) (word mode) device configuration code 1fh (byte mode) device proliferation code (01h) 0fh (dq 815 ) (word mode) device proliferation code (01h) a page buffer swap followed by a page buffer read sequence is necessary to access this information. the contents of all other page buffer locations, after the upload device information command is written, are reserved for future imple- mentation by intel corporation. see section 4.8 for a description of the device configuration code. this code also corresponds to data written to the 28f016sv after writing the ry/by y reconfiguration command. 12. to ensure that the 28f0165v's power consumption during sleep mode reaches the deep power-down current level, the system also needs to de-select the chip by taking either or both ce 0 y or ce 1 y high. 13. the upper byte of the data bus (dq 815 ) during command wntes is a don't care in x16 operation of the device. 15
VS28F016SV, ms28f016sv flashfile tm memory 4.5 compatible status register wsms ess es dws vpps r r r 76543210 notes: csr.7 e write state machine status ry/by y output or wsms bit must be checked to determine completion of an operation (erase, erase 1 e ready suspend, or data write) before the appropriate status bit 0 e busy (ess, es or dws) is checked for success. csr.6 e erase-suspend status 1 e erase suspended 0 e erase in progress/completed csr.5 e erase status if dws and es are set to ``1'' during an erase attempt, an improper command sequence was entered. clear the 1 e error in block erasure csr and attempt the operation again. 0 e successful block erase csr.4 e data-write status 1 e error in data write 0 e data write successful csr.3 e v pp status the vpps bit, unlike an a/d converter, does not provide continuous indication of v pp level. the wsm interrogates 1 e v pp error detect, operation abort v pp 's level only after the data-write or erase command 0 e v pp ok sequences have been entered, and informs the system if v pp has not been switched on. vpps is not guaranteed to report accurate feedback between v pplk (max) and v pph1 (min) and between v pph1 (max) and v pph2 (min) and above v pph 2 (max). csr.2-0 e reserved for future enhancements these bits are reserved for future use; mask them out when polling the csr. 16
VS28F016SV, ms28f016sv flashfile tm memory 4.6 global status register wsms oss dos dss qs pbas pbs pbss 76543210 notes: gsr.7 e write state machine status [ 1 ] ry/by y output or wsms bit must be checked to determine completion of an operation (block lock, 1 e ready suspend, any ry/by y reconfiguration, upload status 0 e busy bits, erase or data write) before the appropriate status bit (oss or dos) is checked for success. gsr.6 e operation suspend status 1 e operation suspended 0 e operation in progress/completed gsr.5 e device operation status 1 e operation unsuccessful 0 e operation successful or currently running gsr.4 e device sleep status 1 e device in sleep 0 e device not in sleep matrix 5/4 00 e operation successful or currently if operation currently running, then gsr.7 e 0. running 01 e device in sleep mode or pending if device pending sleep, then gsr.7 e 0. sleep 10 e operation unsuccessful 11 e operation unsuccessful or aborted operation aborted: unsuccessful due to abort command. gsr.3 e queue status 1 e queue full 0 e queue available gsr.2 e page buffer available status 1 e one or two page buffers available the device contains two page buffers. 0 e no page buffer available gsr.1 e page buffer status 1 e selected page buffer ready 0 e selected page buffer busy selected page buffer is currently busy with wsm operation gsr.0 e page buffer select status 1 e page buffer 1 selected 0 e page buffer 0 selected note: 1. when multiple operations are queued, checking bsr.7 only provides indication of completion for that particular block. gsr.7 provides indication when all queued operations are completed. 17
VS28F016SV, ms28f016sv flashfile tm memory 4.7 block status register bs bls bos boas qs vpps vppl r 76 5 4 3 2 10 notes: bsr.7 e block status [ 1 ] ry/by y output or bs bit must be checked to determine completion of an operation (block lock, 1 e ready suspend, erase or data write) before the appropriate 0 e busy status bits (bos, bls) is checked for success. bsr.6 e block lock status 1 e block unlocked for write/erase 0 e block locked for write/erase bsr.5 e block operation status 1 e operation unsuccessful 0 e operation successful or currently running bsr.4 e block operation abort status 1 e operation aborted the boas bit will not be set until bsr.7 e 1. 0 e operation not aborted matrix 5/4 00 e operation successful or currently running 01 e not a valid combination 10 e operation unsuccessful 11 e operation aborted operation halted via abort command. bsr.3 e queue status 1 e queue full 0 e queue available bsr.2 e v pp status 1 e v pp error detect, operation abort 0 e v pp ok bsr.1 e v pp level bsr.1 is not guaranteed to report accurate feedback between the v pph1 and v pph2 voltage ranges. writes 1 e v pp detected at 5.0v g 10% and erases with v pp between v pplk (max) and v pph1 0 e v pp detected at 12.0v g 5% (min), between v pph1 (max) and v pph2 (min), and above v pph2 (max) produce spurious results and should not be attempted. bsr.1 was a reserved bit on the 28f016sa. bsr.0 e reserved for future enhancements this bit is reserved for future use; mask it out when polling the bsrs. note: 1. when multiple operations are queued, checking bsr.7 only provides indication of completion for that particular block. gsr.7 provides indication when all queued operations are completed. 18
VS28F016SV, ms28f016sv flashfile tm memory 4.8 device configuration code r r r r r rb2 rb1 rb0 76543 2 1 0 notes: dcc.2-dcc.0 e ry/by y configuration (rb2-rb0) undocumented combinations of rb2-rb0 are reserved by intel corporation for future 001 e level mode (default) implementations and should not be used. 010 e pulse-on-write 011 e pulse-on-erase 100 e ry/by y disabled 101 e pulse-on-write/erase dcc.7-dcc.3 e reserved for future enhancements these bits are reserved for future use; mask them out when reading the device configuration code. set these bits to ``0'' when writing the desired ry/by y configuration to the device. 19
VS28F016SV, ms28f016sv flashfile tm memory 5.0 electrical specifications 5.1 absolute maximum ratings * temperature under bias ese1 b 55 cto a 125 c ese2 b 40 cto a 125 c storage temperature b 65 to a 125 c notice: this data sheet contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest data sheet be- fore finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. v cc e 3.3v g 0.15v systems (4) sym parameter notes min max units test conditions t cse2 operating temperature, se2 b 40 a 125 c t cse1 operating temperature, se1 b 55 a 125 c v cc v cc with respect to gnd 1 b 0.2 7.0 v v pp v pp supply voltage with respect to gnd 1,2 b 0.2 14.0 v v voltage on any pin (except v cc ,v pp ) with 1,5 b 0.5 v cc v respect to gnd a 0.5 i current into any non-supply pin 5 g 30 ma i out output short circuit current 3 100 ma v cc e 5.0v g 0.5v, v cc e 5.0v g 0.25v systems (4, 5) sym parameter notes min max units test conditions t cse2 operating temperature, se2 b 40 a 125 c t cse1 operating temperature, se1 b 55 a 125 c v cc v cc with respect to gnd 1 b 0.2 7.0 v v pp v pp supply voltage with respect to gnd 1,2 b 0.2 14.0 v v voltage on any pin (except v cc ,v pp ) with 1,5 b 2.0 7.0 v respect to gnd i current into any non-supply pin 5 g 30 ma i out output short circuit current 3 100 ma notes: 1. minimum dc voltage is b 0.5v on input/output pins. during transitions, this level may undershoot to b 2.0v for periods k 20 ns. maximum dc voltage on input/output pins is v cc a 0.5v which, during transitions, may overshoot to v cc a 2.0v for periods k 20 ns. 2. maximum dc voltage on v pp may overshoot to a 14.0v for periods k 20 ns. 3. output shorted for no more than one second. no more than one output shorted at a time. 4. ac specifications are valid at both voltage ranges. see dc characteristics tables for voltage range-specific specifications. 5. this specification also applies to pin marked ``nc''. 6. 5% v cc specifications refer to the vs/ms28f016sv-80 in its high speed test configuration. 20
VS28F016SV, ms28f016sv flashfile tm memory 5.2 capacitance for a 3.3v g 0.15v system: sym parameter notes typ max units test conditions c in capacitance looking into an 1 6 8 pf t a e 25 c, f e 1.0 mhz address/control pin c out capacitance looking into an 1 8 12 pf t a e 25 c, f e 1.0 mhz output pin c load load capacitance driven by 1,2 50 pf for v cc e 3.3v g 0.15v outputs for timing specifications equivalent load timing circuit 2.5 ns 50 x transmission line delay for a 5.0v system: sym parameter notes typ max units test conditions c in capacitance looking into an 1 6 8 pf t a e 25 c, f e 1.0 mhz address/control pin c out capacitance looking into an 1 8 12 pf t a e 25 c, f e 1.0 mhz output pin c load load capacitance driven by 1,2 100 pf for v cc e 5.0v g 0.5v outputs for timing specifications 30 pf for v cc e 5.0v g 0.25v equivalent testing load circuit for 2.5 ns 25 x transmission line v cc g 10% delay equivalent testing load circuit for 2.5 ns 85 x transmission line v cc g 5% delay notes: 1. sampled, not 100% tested. guaranteed by design. 2. to obtain ibis models for the vs/ms28f016sv, please contact your local intel/distribution sales office. 21
VS28F016SV, ms28f016sv flashfile tm memory 5.3 timing nomenclature all 3.3v system timings are measured from where signals cross 1.5v. for 5.0v systems use the standard jedec cross point definitions. each timing parameter consists of 5 characters. some common examples are defined as follows: t ce t elqv time(t) from ce y (e) going low (l) to the outputs (q) becoming valid (v) t oe t glqv time(t) from oe y (g) going low (l) to the outputs (q) becoming valid (v) t acc t avqv time(t) from address (a) valid (v) to the outputs (q) becoming valid (v) t as t avwh time(t) from address (a) valid (v) to we y (w) going high (h) t dh t whdx time(t) from we y (w) going high (h) to when the data (d) can become un- defined (x) pin characters pin states a address inputs h high d data inputs l low q data outputs v valid ece y (chip enable) x driven, but not necessarily valid f byte y (byte enable) z high impedance goe y (output enable) wwe y (write enable) prp y (deep power-down pin) r ry/by y (ready busy) v any voltage level y 3/5 y pin 5v v cc at 4.5v minimum 3v v cc at 3.15v minimum 22
VS28F016SV, ms28f016sv flashfile tm memory 271312 6 ac test inputs are driven at v oh (2.4 vttl) for a logic ``1'' and v ol (0.45 vttl) for a logic ``0.'' input timing begins at v ih (2.0 vttl) and v il (0.8 vttl). output timing ends at v ih and v il . input rise and fall times (10% to 90%) k 10 ns. figure 6. transient input/output reference waveform for v cc e 5.0v g 10% (standard testing configuration) 271312 7 ac test inputs are driven at 3.15v for a logic ``1'' and 0.0v for a logic ``0.'' input timing begins, and output timing ends, at 1.5v. input rise and fall times (10% to 90%) k 10 ns. figure 7. transient input/output reference waveform (v cc e 3.3v g 0.15v) high speed reference waveform (v cc e 5.0v g 5%) note: 1. testing characteristics for vs/ms28f016sv-085 (standard testing configuration) and vs/ms28f016sv-100. 23
VS28F016SV, ms28f016sv flashfile tm memory 2.5 ns of 25 x transmission line total capacitance e 100 pf 271312 8 figure 8. transient equivalent testing load circuit (v cc e 5.0v g 10%) 2.5 ns of 50 x transmission line total capacitance e 50 pf 271312 9 figure 9. transient equivalent testing load circuit (v cc e 3.3v g 0.15v) 2.5 ns of 83 x transmission line total capacitance e 30 pf 271312 10 figure 10. high speed transient equivalent testing load circuit (v cc e 5.0v g 5%) 24
VS28F016SV, ms28f016sv flashfile tm memory 5.4 dc characteristics v cc e 3.3v g 0.15v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c sym parameter notes min max units test conditions i li input load current 1 g 1 m av cc e v cc max, v in e v cc or gnd i lo output leakage current 1 g 10 m av cc e v cc max, v out e v cc or gnd i ccs v cc standby 1,5 130 m av cc e v cc max, current ce 0 y ,ce 1 y ,rp y e v cc g 0.2v byte y ,wp y , 3/5 y e v cc g 0.2v or gnd g 0.2v 4mav cc e v cc max, ce 0 y ,ce 1 y ,rp y e v ih byte y ,wp y , 3/5 y e v ih or v il i ccd v cc deep power- 1 50 m arp y e gnd g 0.2v down current byte y e v cc g 0.2v or gnd g 0.2v i ccr 1v cc read current 1,4,5 60 ma v cc e v cc max cmos: ce 0 y ,ce 1 y e gnd g 0.2v byte y e gnd g 0.2v or v cc g 0.2v inputs e gnd g 0.2v or v cc g 0.2v ttl: ce 0 y ,ce 1 y e v il , byte y e v il or v ih inputs e v il or v ih , f e 8 mhz, i out e 0ma i ccr 2v cc read current 1,4,5,6 40 ma v cc e v cc max cmos: ce 0 y ,ce 1 y e gnd g 0.2v byte y e gnd g 0.2v or v cc g 0.2v inputs e gnd g 0.2v or v cc g 0.2v ttl: ce 0 y ,ce 1 y e v il , byte y e v il or v ih inputs e v il or v ih , f e 4 mhz, i out e 0ma 25
VS28F016SV, ms28f016sv flashfile tm memory 5.4 dc characteristics (continued) v cc e 3.3v g 0.3v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c sym parameter notes min max units test conditions i ccw v cc write current 1,6 12 ma word/byte write in progress v pp e 12.0v g 5% 17 ma word/byte write in progress v pp e 5.0v g 10% i cce v cc block erase 1,6 12 ma block erase in progress current v pp e 12.0v g 5% 17 ma block erase in progress v pp e 5.0v g 10% i cces v cc erase 1,2 6 ma ce 0 y ,ce 1 y e v ih suspend current block erase suspended i pps v pp standby/read 1 g 100 m av pp s v cc i ppr current 200 m av pp l v cc i ppd v pp deep power- 1 50 m arp y e gnd g 0.2v down current i ppw v pp write current 1 15 ma v pp e 12.0v g 5% word/byte write in progress 25 ma v pp e 5.0v g 10% word/byte write in progress i ppe v pp erase current 1 10 ma v pp e 12.0v g 5% block erase in progress 20 ma v pp e 5.0v g 10% block erase in progress i ppes v pp erase 1 200 m av pp e v pph1 or v pph2 , suspend current block erase suspended v il input low voltage b 0.3 0.8 v v ih input high voltage v cc 2.0 a v 0.3 v ol output low 0.4 v v cc e v cc min and voltage i ol e 4ma 26
VS28F016SV, ms28f016sv flashfile tm memory 5.4 dc characteristics (continued) v cc e 3.3v g 0.15v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c sym parameter notes min max units test conditions v oh 1 output high 2.4 v i oh eb 2.0 ma voltage v cc e v cc min v oh 2v cc b 0.2 v i oh eb 100 m a v cc e v cc min v pplk v pp erase/write 3 0.0 1.8 v lock voltage v pph1 v pp during 3 4.5 5.5 v write/erase operations v pph2 v pp during 3 11.4 12.6 v write/erase operations v lko v cc erase/write 1.8 v lock voltage notes: 1. all currents are in rms unless otherwise noted. these currents are valid for all product versions (package and speeds). 2. i cces is specified with the device de-selected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr . 3. block erases, word/byte writes and lock block operations are inhibited when v pp s v pplk and not guaranteed in the ranges between v pplk (max) and v pph1 (min), between v pph1 (max) and v pph2 (min) and above v pph2 (max). 4. automatic power savings (aps) reduces i ccr to less than 3 ma in static operation. 5. cmos inputs are either v cc g 0.2v or gnd g 0.2v. ttl inputs are either v il or v ih . 6. sampled, but not 100% tested. guaranteed by design. 27
VS28F016SV, ms28f016sv flashfile tm memory 5.5 dc characteristics v cc e 5.0v g 0.5v, 5.0v g 0.25v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c sym parameter notes min max units test conditions i li input load current 1 g 1 m av cc e v cc max v in e v cc or gnd i lo output leakage 1 g 10 m av cc e v cc max current v in e v cc or gnd i ccs v cc standby 1,5 130 m av cc e v cc max current ce 0 y ,ce 1 y ,rp y e v cc g 0.2v byte y ,wp y e v cc g 0.2v or gnd g 0.2v 4mav cc e v cc max ce 0 y ,ce 1 y ,rp y e v ih byte y ,wp y , 3/5 y e v ih or v il i ccd v cc deep power- 1 50 m arp y e gnd g 0.2v down current byte y e v cc g 0.2v or gnd g 0.2v i ccr 1v cc read current 1,4,5 135 ma v cc e v cc max, cmos:ce 0 y ,ce 1 y e gnd g 0.2v byte y e gnd g 0.2v or v cc g 0.2v inputs e gnd g 0.2v or v cc g 0.2v ttl: ce 0 y ,ce 1 y e v il , byte y e v il or v ih, inputs e v il or v ih , f e 10 mhz, i out e 0ma i ccr 2v cc read current 1,4,5,6 90 ma v cc e v cc max, cmos:ce 0 y ,ce 1 y e gnd g 0.2v byte y e gnd g 0.2v or v cc g 0.2v inputs e gnd g 0.2v or v cc g 0.2v ttl: ce 0 y ,ce 1 y e v il , byte y e v il or v ih , inputs e v il or v ih , f e 5 mhz, i out e 0ma 28
VS28F016SV, ms28f016sv flashfile tm memory 5.5 dc characteristics (continued) v cc e 5.0v g 0.5v, 5.0v g 0.25v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c sym parameter notes min max units test conditions i ccw v cc write current 1,6 35 ma word/byte in progress v pp e 12.0v g 5% 40 ma word/byte in progress v pp e 5.0v g 10% i cce v cc block erase 1,6 25 ma block erase in progress current v pp e 12.0v g 5% 30 ma block erase in progress v pp e 5.0v g 10% i cces v cc erase 1,2 10 ma ce 0 y ,ce 1 y e v ih suspend current block erase suspended i pps v pp standby/read 1 g 100 m av pp s v cc i ppr current 200 m av pp l v cc i ppd v pp deep power- 1 50 m arp y e gnd g 0.2v down current i ppw v pp write current 1,6 12 ma v pp e 12.0v g 5% word/byte write in progress 22 ma v pp e 5.0v g 10% word/byte write in progress i ppe v pp block erase 1,6 10 ma v pp e 12.0v g 5% current block erase in progress 20 ma v pp e 5.0v g 10% block erase in progress i ppes v pp erase 1 200 m av pp e v pph1 or v pph2 , suspend current block erase suspended v il input low voltage 6 b 0.5 0.8 v v ih input high voltage 6 2.0 v cc v a 0.5 29
VS28F016SV, ms28f016sv flashfile tm memory 5.5 dc characteristics (continued) v cc e 5.0v g 0.5v, 5.0v g 0.25v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c sym parameter notes min max units test conditions v ol output low 6 0.45 v v cc e v cc min voltage i ol e 5.8 ma v oh 1 output high 6 0.85 v i oh eb 2.5 ma voltage v cc v cc e v cc min v oh 26v cc i oh eb 100 m a b 0.4 v cc e v cc min v pplk v pp write/erase 3,6 0.0 1.8 v lock voltage v pph1 v pp during 4.5 5.5 v write/erase operations v pph2 v pp during 11.4 12.6 v write/erase operations v lko v cc write/erase 1.8 v lock voltage notes: 1. all currents are in rms unless otherwise noted. these currents are valid for all product versions (package and speeds). 2. i cces is specified with the device de-selected. if the device is read while in erase suspend mode, current draw is the sum of i cces and i ccr. 3. block erases, word/byte writes and lock block operations are inhibited when v pp s v pplk and not guaranteed in the ranges between v pplk (max) and v pph1 (min), between v pph1 (max) and v pph2 (min) and above v pph2 (max). 4. automatic power saving (aps) reduces i ccr to less than 1 ma in static operation. 5. cmos inputs are either v cc g 0.2v or gnd g 0.2v. ttl inputs are either v il or v ih . 6. sampled, not 100% tested. guaranteed by design. 30
VS28F016SV, ms28f016sv flashfile tm memory 5.6 ac characteristicseread only operations (1) v cc e 3.3v g 0.15v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 50 pf versions units sym parameter notes min max t avav read cycle time 120 ns t avqv address to output delay (t acc ) 120 ns t elqv ce y to output delay (t ce ) 2,7 120 ns t phqv rp y high to output delay 620 ns t glqv oe y to output delay (t oe ) 2 45 ns t elqx ce y to output in low z 3,7 0 ns t ehqz ce y to output in high z 3,7 50 ns t glqx oe y to output in low z 3 0 ns t ghqz oe y to output in high z 3 30 ns t oh output hold from address, ce y or oe y 3,7 0 ns change, whichever occurs first t flqv byte y to output delay 3 120 ns t fhqv t flqz byte y low to output in high z 3 30 ns t elfl ce y low to byte y high or low 3,7 5 ns t elfh extended status register reads sym parameter notes min max units t avel address setup to ce y going low 3,7,8,9 0 ns t avgl address setup to oe y going low 3,7,9 0 ns 31
VS28F016SV, ms28f016sv flashfile tm memory 5.6 ac characteristicseread only operations (1) (continued) v cc e 5.0v g 0.25v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 30 pf v cc e 5.0v g 0.5v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 100 pf versions (4) vs/ms28f016sv-85 vs/ms28f016sv-85 vs/ms28f016sv-100 unit v cc g 5% (5) v cc g 10% (6) v cc g 10% sym parameter notes min max min max min max t avav read cycle time 80 85 100 ns t avqv address to output 80 85 100 ns delay (t acc ) t elqv ce y to output 2 80 85 100 ns delay (t ce ) t phqv rp y to output 400 480 480 ns delay t glqv oe y to output 2 30 35 40 ns delay (t oe ) t elqx ce y to output in 3 0 0 0 ns low z t ehqz ce y to output in 3 25 30 35 ns high z t glqx oe y to output in 3 0 0 0 ns low z t ghqz oe y to output in 3 25 30 35 ns high z t oh output hold from 3 0 0 0 ns address, ce y or oe y change, whichever occurs first t flqv byte y to output 3 80 85 100 ns delay t fhqv t flqz byte y low to 3 25 30 35 ns output in high z t elfl ce y low to 3 5 5 5 ns byte y high or t elfh low extended status register reads sym parameter notes min max min max min max unit t avel address setup to ce y going 3,7,8,9 0 0 0 ns low t avgl address setup to oe y going 3,7,9 0 0 0 ns low 32
VS28F016SV, ms28f016sv flashfile tm memory notes: 1. see ac input/output reference waveforms for timing measurements, figures 6 and 7. 2. oe y may be delayed up to t elqv t glqv after the falling edge of ce y , without impacting t elqv . 3. sampled, not 100% tested. guaranteed by design. 4. device speeds are defined as: 80/85, 100 ns at v cc e 5.0v equivalent to 120 ns at v cc e 3.3v 5. see the high speed ac input/output reference waveforms and ac testing load circuit. 6. see the standard ac input/output reference waveforms and ac testing load circuit. 7. ce x y is defined as the latter of ce 0 y or ce 1 y going low, or the f. 8. this timing parameter is used to latch the correct bsr data onto the outputs. 9. the address setup requirement for extended status register reads must only be met referenced to the falling edge of the last control signal to become active (ce 0 y ,ce 1 y ,oroe y ). for example, if ce 0 y or ce 1 y are activated prior to oe y for an extended status register read, specification t avgl must be met. on the other hand, if either ce 0 y or ce 1 y (or both) are activated after oe y , specification t avel must be referenced. 271312 11 note: cex y is defined as the latter of ce 0 y or ce 1 y going low, or the first of ce 0 y or ce 1 y going high. figure 11. read timing waveforms 33
VS28F016SV, ms28f016sv flashfile tm memory 271312 12 note: cex y is defined as the latter of ce 0 y or ce 1 y going low, or the first of ce 0 y or ce 1 y going high. figure 12. byte y timing waveforms 34
VS28F016SV, ms28f016sv flashfile tm memory 5.7 power-up and reset timings 271312 22 figure 13. v cc power-up and rp y reset waveforms symbol parameter notes min max unit t plyl rp y low to 3/5 y low (high) 0 m s t plyh t ylph 3/5 y low (high) to rp y high 1 2 m s t yhph t pl5v rp y low to v cc at 4.5v minimum (to v cc at 3.0v min or 2 0 m s 3.6v max) t pl3v t phel3 rp y high to ce y low (3.3v v cc ) 1 405 ns t phel5 rp y high to ce y low (5v v cc ) 1 330 ns t avqv address valid to data valid for v cc e 5v g 10% 3 70 ns t phqv rp y high to data valid for v cc e 5v g 10% 3 400 ns notes: ce 0 y ,ce 1 y and oe y are switched low after power-up. 1. the t ylph and/or t yhph times must be strictly followed to guarantee all other read and write specifications for the vs/ms28f016sv. 2. the power supply may start to switch concurrently with rp y going low. 3. the address access time and rp y high to data valid time are shown for 5.0v v cc operation of the 28f016sv-085 (standard test configuration). refer to the ac chracteristicseread only operations for 3.3v v cc and 5.0v v cc (high speed test configuration) values. 35
VS28F016SV, ms28f016sv flashfile tm memory 5.8 ac characteristics for we y econtrolled command write operations (1) v cc e 3.3v g 0.15v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 50 pf versions unit sym parameter notes min max t avav write cycle time 120 ns t vpwh (1,2) v pp setup to we y going high 3 100 ns t phel rp y setup to ce y going low 3,7 480 ns t elwl ce y setup to we y going low 3,7 10 ns t avwh address setup to we y going high 2,6 75 ns t dvwh data setup to we y going high 2,6 75 ns t wlwh we y pulse width 75 ns t whdx data hold from we y high 2 10 ns t whax address hold from we y high 2 10 ns t wheh ce y hold from we y high 3,7 10 ns t whwl we y pulse width high 45 ns t ghwl read recovery before write 3 0 ns t whrl we y high to ry/by y going low 3 100 ns t rhpl rp y hold from valid status register (csr, 3 0 ns gsr, bsr) data and ry/by y high t phwl rp y high recovery to we y going low 3 480 ns t whgl write recovery before read 95 ns t qvvl (1,2) v pp hold from valid status register (csr, 3 0 m s gsr, bsr) data and ry/by y high t whqv (1) duration of word/byte write operation 3,4,5,11 5 m s t whqv (2) duration of block erase operation 3,4 0.3 10 sec 36
VS28F016SV, ms28f016sv flashfile tm memory 5.8 ac characteristics for we y econtrolled command write operations (1) (continued) v cc e 5.0v g 0.25v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 30 pf v cc e 5.0v g 0.5v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 100 pf versions vs/ms28f016sv-85 vs/ms28f016sv-85 vs/ms28f016sv-100 unit v cc g 5% v cc g 10% v cc g 10% sym parameter notes min max min max min max t avav write cycle 80 85 100 ns time t vpwh (1) v pp setup to 3 100 100 100 ns we y going t vpwh (2) high t phel rp y setup to 3,7 480 480 480 ns ce y going low t elwl ce y setup to 3,7 0 0 0 ns we y going low t avwh address 2,6 50 50 50 ns setup to we y going high t dvwh data setup to 2,6 50 50 50 ns we y going high t wlwh we y pulse 50 60 70 ns width t whdx data hold 2 10 10 10 ns from we y high t whax address hold 2 10 10 10 ns from we y high t wheh ce y hold 3,7 10 10 10 ns from we y high t whwl we y pulse 30 30 30 ns width high t ghwl read 3 0 0 0 ns recovery before write t whrl we y high to 3 100 100 100 ns ry/by y going low t rhpl rp y hold 3 0 0 0 ns from valid status register (csr, gsr, bsr) data and ry/by y high 37
VS28F016SV, ms28f016sv flashfile tm memory 5.8 ac characteristics for we y econtrolled command write operations (1) v cc e 5.0v g 0.25v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 30 pf v cc e 5.0v g 0.5v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 100 pf (continued) versions vs/ms28f016sv-85 vs/ms28f016sv-85 vs/ms28f016sv-100 unit v cc g 5% v cc g 10% v cc g 10% sym parameter notes min max min max min max t phwl rp y high 3 1 1 1 m s recovery to we y going low t whgl write 60 65 70 ns recovery before read t qvvl (1) v pp hold 3 0 0 0 m s from valid t qvvl (2) status register (csr, gsr, bsr) data and ry/ by y high t whqv (1) duration of 3,4,5,11 4.5 4.5 4.5 m s word/byte write operation t whqv (2) duration of 3,4 0.3 10 0.3 10 0.3 10 sec block erase operation notes: 1. read timings during write and erase are the same as for normal read. 2. refer to command definition tables for valid address and data values. 3. sampled, not 100% tested. guaranteed by design. 4. write/erase durations are measured to valid status register (csr) data. v pp e 12.0v g 0.6v 5. word/byte write operations are typically performed with 1 programming pulse. 6. address and data are latched on the rising edge of we y for all command write operations. 7. ce x y is defined as the latter of ce 0 y or ce 1 y going low, or the first of ce 0 y or ce 1 y going high. 8. device speeds are defined as: 80/85, 100 ns at v cc e 5.0v equivalent to 120 ns at v cc e 3.3v 9. see the high speed ac input/output reference waveforms and ac testing load circuit. 10. see the standard ac input/output reference waveforms and ac testing load circuit. 11. the tbd information will be available in a technical paper. please contact intel's application hotline or your local sales office for more information. 38
VS28F016SV, ms28f016sv flashfile tm memory 271312 23 notes: 1. this address string depicts data write/erase cycles with corresponding verification via esrd. 2. this address string depicts data write/erase cycles with corresponding verification via csrd. 3. this cycle is invalid when using csrd for verification during data write/erase operations. 4. cex y is defined as the latter of ce 0 y or ce 1 y going low or the first of ce 0 y or ce 1 y going high. 5. rp y low transition is only to show t rhpl ; not valid for above read and write cycles. 6. v pp voltage during write/erase operations valid at both 12.0v and 5.0v. 7. v pp voltage equal to or below v pplk provides complete flash memory array protection. figure 14. ac waveforms for command write operations 39
VS28F016SV, ms28f016sv flashfile tm memory 5.9 ac characteristics for ce y econtrolled command write operations (1) v cc e 3.3v g 0.15v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 50 pf versions unit sym parameter notes min max t avav write cycle time 120 ns t phwl rp y setup to we y going low 3 480 ns t vpeh (1,2) v pp setup to ce y going high 3,7 100 ns t wlel we y setup to ce y going low 3,7 0 ns t aveh address setup to ce y going high 2,6,7 75 ns t dveh data setup to ce y going high 2,6,7 75 ns t eleh ce y pulse width 7 75 ns t ehdx data hold from ce y high 2,7 10 ns t ehax address hold from ce y high 2,7 10 ns t ehwh we y hold from ce y high 3 10 ns t ehel ce y pulse width high 7 45 ns t ghel read recovery before write 3 0 ns t ehrl ce y high to ry/by y going low 3,7 100 ns t rhpl rp y hold from valid status register (csr, 3 0 ns gsr, bsr) data and ry/by y high t phel rp y high recovery to ce y going low 3,7 480 ns t ehgl write recovery before read 95 ns t qvvl (1,2) v pp hold from valid status register (csr, 3 0 m s gsr, bsr) data and ry/by y high t ehqv (1) duration of word/byte write operation 3,4,5,11 5 m s t ehqv (2) duration of block erase operation 4 0.3 10 sec 40
VS28F016SV, ms28f016sv flashfile tm memory 5.9 ac characteristics for ce y econtrolled command write operations (1) (continued) v cc e 5.0v g 0.25v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 30 pf v cc e 5.0v g 0.5v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 100 pf versions (4) vs/ms28f016sv-85 vs/ms28f016sv-85 vs/ms28f016sv-100 v cc g 5% v cc g 10% v cc g 10% unit sym parameter notes min max min max min max t avav write cycle 80 85 100 ns time t phwl rp y setup to 3 480 480 480 ns we y going low t vpeh (1,2) v pp setup to 3,7 100 100 100 ns ce y going high t wlel we y setup to 3,7 0 0 0 ns ce y going low t aveh address setup 2,6,7 50 50 50 ns to ce y going high t dveh data setup to 2,6,7 50 50 50 ns ce y going high t eleh ce y pulse 7 50 60 70 ns width t ehdx data hold from 2,7 10 10 10 ns ce y high t ehax address hold 2,7 10 10 10 ns from ce y high t ehwh we hold from 3,7 10 10 10 ns ce y high t ehel ce y pulse 7 30 30 30 ns width high t ghel read recovery 3 0 0 0 ns before write t ehrl ce y high to 3,7 100 100 100 ns ry/by y going low t rhpl rp y hold from 3 0 0 0 ns valid status register (csr, gsr, bsr) data and ry/by y high 41
VS28F016SV, ms28f016sv flashfile tm memory 5.9 ac characteristics for ce y econtrolled command write operations (1) v cc e 5.0v g 0.25v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 30 pf v cc e 5.0v g 0.5v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 100 pf (continued) versions (4) vs/ms28f016sv-85 vs/ms28f016sv-85 vs/ms28f016sv-100 v cc g 5% v cc g 10% v cc g 10% unit sym parameter notes min max min max min max t phel rp y high 3,7 1 1 1 m s recovery to ce y going low t ehgl write 60 65 70 ns recovery before read t qvvl (1,2) v pp hold 3 0 0 0 m s from valid status register (csr, gsr, bsr) data at ry/by y high t ehqv (1) duration of 3,4,5,11 4.5 4.5 4.5 m s word/byte write operation t ehqv (2) duration of 3,4 0.3 10 0.3 10 0.3 10 sec block erase operation notes: 1. read timings during write and erase are the same as for normal read. 2. refer to command definition tables for valid address and data values. 3. sampled, not 100% tested. guaranteed by design. 4. write/erase durations are measured to valid status data. v pp e 12.0v g 0.6v. 5. word/byte write operations are typically performed with 1 programming pulse. 6. address and data are latched on the rising edge of ce y for all command write operations. 7. ce x y is defined as the latter of ce 0 y or ce 1 y going low, or the first of ce 0 y or ce 1 y going high. 8. device speeds are defined as: 80/85, 100 ns at v cc e 5.0v equivalent to 120 ns at v cc e 3.3v 9. see the high speed ac input/output reference waveforms and ac testing load circuit. 10. see the standard ac input/output reference waveforms and ac testing load circuit. 11. the tbd information will be available in a technical paper. please contact intel's application hotline or your local sales office for more information. 42
VS28F016SV, ms28f016sv flashfile tm memory 271312 24 notes: 1. this address string depicts data-write/erase cycles with corresponding verification via esrd. 2. this address string depicts data-write/erase cycles with corresponding verification via csrd. 3. this cycle is invalid when using csrd for verification during data write/erase operations. 4. cex y is defined as the latter of ce 0 y or ce 1 y going low or the first of ce 0 y or ce 1 y going high. 5. rp y low transition is only to show t rhpl ; not valid for above read and write cycles. 6. v pp voltage during write/erase operations valid at both 12.0v and 5.0v. 7. v pp voltage equal to or below v pplk provides complete flash memory array protection. figure 15. alternate ac waveforms for command write operations 43
VS28F016SV, ms28f016sv flashfile tm memory 5.10 ac characteristics for we y econtrolled page buffer write operations (1) v cc e 3.3v g 0.3v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 50 pf versions 28f016sv-120 unit sym parameter notes min typ max t avwl address setup to we y going low 2 25 ns v cc e 5.0v g 0.5v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 50 pf versions (3) v cc g 5% 28f016sv-080 (4) unit v cc g 10% 28f016sv-080 (5) 28f016sv-085 (5) sym parameter notes min typ max min typ max t avwl address setup 2 15 15 ns to we y going low notes: 1. all other specifications for we y econtrolled write operations can be found in section 5.8. 2. address must be valid during the entire we y low pulse. 3. device speeds are defined as: 80/85, 100 ns at v cc e 5.0v equivalent to 120 ns at v cc e 3.3v 4. see the high speed ac input/output reference waveforms and ac testing load circuit. 5. see the standard ac input/output reference waveforms and ac testing load circuit. 44
VS28F016SV, ms28f016sv flashfile tm memory 271312 25 note: 1. ce x y is defined as the latter of ce 0 y or ce 1 y going low, or the first of ce 0 y or ce 1 y going high. figure 16. we y econtrolled page buffer write timing waveforms (loading data to the tape buffer) 45
VS28F016SV, ms28f016sv flashfile tm memory 5.11 ac characteristics for ce y econtrolled page buffer write operations (1) v cc e 3.3v g 0.3v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 50 pf versions 28f016sv-120 unit sym parameter notes min typ max t avel address setup to ce y going low 2, 3 25 ns v cc e 5.0v g 0.5v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c, load e 50 pf versions (4) v cc g 5% 28f016sv-080 (5) unit v cc g 10% 28f016sv-080 (6) 28f016sv-085 (6) sym parameter notes min typ max min typ max t avel address setup 2, 3 15 15 ns to ce y going low notes: 1. all other specifications for ce y econtrolled write operations can be found in section 5.9. 2. address must be valid during the entire ce y low pulse. 3. cex y is defined as the latter of ce 0 y or ce 1 y going low, or the first of ce 0 y or ce 1 y going high. 4. device speeds are defined as: 80/85, 100 ns at v cc e 5.0v equivalent to 120 ns at v cc e 3.3v 5. see the high speed ac input/output reference waveforms and ac testing load circuit. 6. see the standard ac input/output reference waveforms and ac testing load circuit. 271312 26 note: 1. cex y is defined as the latter of ce 0 y or ce 1 y going low, or the first of ce 0 y or ce 1 y going high. figure 17. controller page buffer write timing waveforms (loading data to the page buffer) 46
VS28F016SV, ms28f016sv flashfile tm memory 5.12 erase and word/byte write performance (3,5) v cc e 3.3v g 0.15v, v pp e 5.0v g 0.5v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c sym parameter notes typ (1) units test conditions page buffer byte write time 2,6,7 8 m s page buffer word write time 2,6,7 16 m s t whrh 1a byte write time 2,7 29 m s t whrh 1b word write time 2,7 35 m s t whrh (2) block write time 2,7 1.9 sec byte write mode t whrh (3) block write time 2,7 1.2 sec word write mode block erase time 2,7 1.4 sec full chip erase time 2,7 44.8 sec erase suspend latency time 4 12 m s to read auto erase suspend latency 15 m s time to write v cc e 3.3v g 0.15v, v pp e 12.0v g 0.6v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c sym parameter notes typ (1) units test conditions page buffer byte write time 2,6,7 2.2 m s page buffer word write time 2,6,7 4.4 m s t whrh (1) word/byte write time 2,7 9 m s t whrh (2) block write time 2,7 0.6 sec byte write mode t whrh (3) block write time 2,7 0.3 sec word write mode block erase time 2 0.8 sec full chip erase time 2,7 25.6 sec erase suspend latency time 4 9 m s to read auto erase suspend latency 12 m s time to write 47
VS28F016SV, ms28f016sv flashfile tm memory 5.12 erase and word/byte write performance (3,5) (continued) v cc e 5.0v, v pp e 5.0v g 0.5v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c sym parameter notes typ (1) units test conditions page buffer byte write time 2,6,7 8 m s page buffer word write time 2,6,7 16 m s t whrh 1a byte write time 2,7 20 m s t whrh 1b word write time 2,7 25 m s t whrh (2) block write time 2,7 1.4 sec byte write mode t whrh (3) block write time 2,7 0.85 sec word write mode block erase time 2,7 1.0 sec full chip erase time 2,7 32.0 sec erase suspend latency time 4 9 m s to read auto erase suspend latency 12 m s time to write v cc e 5.0v g 0.5v, v pp e 12.0v g 0.6v, t cse2 eb 40 cto a 125 c, t cse1 eb 55 cto a 125 c sym parameter notes typ (1) units test conditions page buffer byte write time 2,6,7 2.1 m s page buffer word write time 2,6,7 4.1 m s t whrh (1) word/byte write time 2,7 6 m s t whrh (2) block write time 2,7 0.4 sec byte write mode t whrh (3) block write time 2,7 0.2 sec word write mode block erase time 2 0.6 sec full chip erase time 2,7 19.2 sec erase suspend latency time 4 7 m s to read auto erase suspend latency 10 m s time to write notes: 1. 25 c, and normal voltages. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. specification applies to interrupt latency for single block erase. suspend latency for erase all unlocked blocks operation extends the maximum latency time to 270 m s. 5. sampled, but not 100% tested. guaranteed by design. 6. assumes using the full page buffer to write to flash (256 bytes or 128 words). 48
VS28F016SV, ms28f016sv flashfile tm memory 6.0 mechanical specifications 271312 27 figure 18. mechanical specifications of the vs/ms28f0165v 56-lead ssop package family: shrink small out-line package symbol millimeters notes minimum nominal maximum a 1.80 1.90 a1 0.47 0.52 0.57 a2 1.18 1.28 1.38 b 0.25 0.30 0.40 c 0.13 0.15 0.20 d 23.40 23.70 24.00 e 13.10 13.30 13.50 e 1 0.80 h e 15.70 16.00 16.30 n56 l 1 0.45 0.50 0.55 y 0.10 a2 3 4 b3 4 5 r1 0.45 0.20 0.25 r2 0.15 0.20 0.25 49
VS28F016SV, ms28f016sv flashfile tm memory device nomenclature v s28f016sve85 m s28f016sve85 ll l l v e se2 s e ssop l access speed m e se1 sv e smartvoltage technology depending on system design specifcations, the vs/ms28f016sv-85 is capable of supporting e 85 ns access time with a v cc of 5.0v g 10% and loading of 100 pf e 100 ns access time with a v cc of 5.0v g 10% and loading of 100 pf additional information order number document/tool 297372 16-mbit flash product family user's manual 292163 ap-610 ``flash memory in-system code and data update techinques'' 292144 ap-393 ``28f016sv compatibility with 28f016sa'' 292127 ap-378 ``system optimization using the enhanced features of the 28f016sa'' 292126 ap-377 ``16-mbit flash product family software drivers, 28f016sa/ 28f016sv/28f016xs/28f016xd'' 292124 ap-387 ``upgrade considerations from the 28f008sa to the 28f016sa'' 292123 ap-374 ``flash memory write protection techniques'' 292092 ap-357 ``power supply solutions for flash memory'' 292165 ab-62 ``compiling optimized code for embedded flash ram memories'' 294016 er-33 ``etox tm flash memory technologyeinsight to intel's fourth generation process innovation'' 297508 flashbuilder utility contact intel/distribution flash cycling utility sales office contact intel/distribution 28f016sv ibis models sales office contact intel/distribution 28f016sv vhdl/verilog models sales office contact intel/distribution 28f016sv timing designer library files sales office contact intel/distribution 28f016sv orcad and viewlogic schematic symbols sales office data sheet revision history number description 001 original version intel corporation, 2200 mission college blvd., santa clara, ca 95052; tel. (408) 765-8080 printed in u.s.a./xxxx/1295/b10m/xx xx

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